Draper Laboratory Engineering Solutions to Problems of National Significance  

 
 
 
Patents

The following are abstracts of U.S. patents issued to Draper Laboratory in this year. Full texts of patents are available through the U.S. Patent Office. Contact information for Draper's Technology Licensing Office is available on the Technology Transfer page.

2000

Links to abstracts of patents published in:
2008 | 2007 | 2006 | 2005 | 2004 | 2003 | 2002 | 2001 | 2000 | 1999 | 1998 | 1997

Pelagic free swimming aquatic vehicle
Method and apparatus for the generation of charged carriers in semiconductor devices
Motor amplitude control circuit in conductor-on-insulator tuning fork gyroscope
Micromachined piezoelectric transducer
Intergrated circuit die assembly
Reliable wafer-scale integrated computing systems

Abstract

Pelagic free swimming aquatic vehicle
Patent # U.S. 6,138,604; Date Issued: October 31, 2000

A pelagic free swimming aquatic vehicle includes a rigid forebody having a predetermined volume; a watertight chamber in the forebody; and a flexible afterbody having a lesser volume than the forebody and including a maneuvering and propulsion propulsion structure and a drive system for driving the structure with a traveling sinusoidal wave motion.

 

Abstract

Method and apparatus for the generation of charged carriers in semiconductor devices
Patent # U.S. 6,084,173; Date Issued: July 4, 2000

A technique for enhancing the generation of carriers (ex. electrons and/or holes) in semiconductor devices such as photovoltaic cells and the like, receiving radiation from a heated surface, through the use of micron juxtaposition of the surface of the device and the heated surface and with the gap thereinbetween preferably evacuated.

 

Abstract

Motor amplitude control circuit in conductor-on-insulator tuning fork gyroscope
Patent # U.S. 6,064,169; Date Issued: May 16, 2000

A control system for a tuning fork gyroscope uses motor frequency to control motor amplitude. The tuning fork gyroscope has a drive signal input and an output signal from which motor frequency is determined. A phase/frequency detector generates an error signal by comparing the actual oscillation phase of the output signal with the phase of a reference signal from a crystal controlled frequency synthesizer. The error signal is filtered in a feedback loop control to reduce phase detector ripple. The output of the loop controller is then used to determine the appropriate drive signal to drive the error signal to a constant and maintain a predetermined oscillation frequency.

 

Abstract

Micromachined piezoelectric transducer
Patent # U.S. 6,028,389; Date Issued: February 22, 2000

A micromachined piezoelectric acoustic transducer includes a substrate; at least one piezoelectric actuator means attached at at least one proximal edge to the substrate; a gap around at least a portion of the remaining edges of the piezoelectric actuator means; and a flexible corrugated membrane in at least a portion of the gap and interconnecting the actuator means with at least one of the substrate or a neighboring actuator means.

 

Abstract

Intergrated circuit die assembly
Patent # U.S. 6,020,646; Date Issued: February 1, 2000

An integrated circuit (IC) die carrier assembly includes a thinned IC die mounted to a substrate or carrier. The IC die is mounted to the carrier via a thin layer of glass. The carrier facilitates fixturing and provides support during the lapping process used to thin the die. Ball bonding, wire bonding, thin film or thick film conductors can be used to interconnect the pads on the IC die to the pads on the carrier. The coefficients of the thermal expansion of the IC die and the carrier are closely matched to avoid damage to the IC die due to uneven expansion of the thinned IC die relative to the carrier. The IC die carrier assembly is better suited for ultrahigh vacuum and high temperature environments than conventional IC die carrier assemblies.

 

Abstract

Reliable wafer-scale integrated computing systems
Patent # U.S. 6,018,812 ; Date Issued: January 25, 2000

Wafer scale integrated circuitry which uses a cluster of wafer components, each component having a plurality of processing elements and a network element connected thereto for controlling the transfer of information to and from the processing elements. The network element is connected to network elements of other wafer components of the cluster for controlling the transfer of information to and from such other network elements. One or more redundant groups of processing elements are formed on the wafer components of the cluster, each redundant group being configured so that the processing elements in the group reside on different ones of the wafer components.