Research Topics

Integrated Circuits and MEMS devices require packages to provide environmental isolation and to connect the tightly spaced electrical contacts on the integrated circuit or MEMS device with the larger feature sizes found on most printed circuit boards. Draper is interested in R&D for advanced packaging  (e.g. hybrid bonding, 3D designs, integrated passive devices) which enables higher density connectivity, allows for the heterogeneous integration of multiple die including 3rd party die, as well as the capability to form complex standalone microelectronics (ME) systems. 

Draper provides hardened-electronic capabilities for applications ranging from quantum computing, spacecraft hardware, safety critical systems, secure systems, and avionics. Engineering solutions need to encompass mission critical, high reliability electronics for the harshest environments including high temperature and radiation. Full lifecycle efforts executed at Draper address these challenges by implementing advanced PCBs, MEMS, multi-chip modules, system-on-chip, and custom ASIC designs for: analog, digital, mixed-signal and RF components.

Draper is looking for Design Tool R&D that focuses on incorporating security and resiliency from the earliest stages of development through product or program execution, which includes secure toolchains and languages as well as developing a library of components to standardize the design process. Techniques to significantly scale formal verification of the hardware design, characterize side-channel pre-silicon, evaluate fault-injection resiliency, and perform reverse engineering of the entire compute stack are also of interest. This includes tools for: (i) incorporating safety, security, and reliability as first class design optimization parameters from specification all the way to layout, (ii)explainable and verifiable AI and ML technologies, and (iii) mitigation of supply-chain risks.

Draper is interested in techniques to design, implement, and evaluate compute stacks that can guarantee security, safety, and reliability of the system – from transistors to applications – in the presence of adversarial attacks or natural occurring phenomena (e.g., radiation). This includes technologies to significantly scale formal verification of the entire compute stack, characterize side-channel (pre- and post-silicon), evaluate fault-injection resiliency, secure the boot process against quantum-based attacks, and perform circumvention and recovery.